As the semiconductor devices keeps scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistors (FinFETs), have been developed to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the conducting channel that is formed by the fin further provides a better electrical control over the channel.
Currently, fabrication of FinFETs always has yield loss issue due to considerable leakage current (Ioff) resulted from unstable process and/or less process window. Accordingly, how to improve the yield loss issue due to considerable leakage current (Ioff) is important.